Design and optimization of 5 × 5 Network on the securing router with integrated SHA-3 & AES core in FPGA for wearable applications

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dc.contributor.authorAl-Sharea, Sara AbdulHaleem Nori
dc.contributor.authorÇevik, Mesut
dc.date.accessioned2025-10-13T12:32:54Z
dc.date.available2025-10-13T12:32:54Z
dc.date.issued2025
dc.departmentEnstitüler, Lisansüstü Eğitim Enstitüsü, Elektrik ve Bilgisayar Mühendisliği Ana Bilim Dalı
dc.description.abstractNetwork-on-Chip (NoC) has been a scalable and effective communication platform for contemporary multi-core systems, providing high-speed data exchange among IP cores with optimized power usage and security. Conventional NoC designs are plagued by latency bottlenecks and security issues, especially in wearable devices, where low power, real-time processing, and data confidentiality are essential. The current work introduces a 5 × 5 NoC router designed specifically for secure, low-power wearable systems, that employs AES-128 encryption and SHA-3 hashing to achieve end-to-end data integrity and confidentiality. Cryptographic cores are provided at the NI level based on pipeline-based encryption to minimize the processing overhead. The suggested FPGA-based NoC design reduces the utilization of logic gates by 10%, increases the speed of data processing by 5%, and decreases power consumption by 20%, which is suitable for resource-limited situations. Performance measurement under mixed traffic loads reveals that at a 1 Gbps injection rate, the system supports an end-to-end aggregate throughput of 1.05 Gbps with reduced flit transmission latency by 25% (from 120 to 90 ns) over traditional NoCs. The system also provides improved security with minimal degradation in throughput and a balance among data protection, performance, and power efficiency. These optimizations make the suggested secure NoC a strong candidate to implement real-time, low-power applications in wearable and IoT settings.
dc.identifier.citationAl-Sharea, S. A. N., & Çevik, M. (2025). Design and optimization of 5× 5 Network on the securing router with integrated SHA-3 & AES core in FPGA for wearable applications. Discover Computing, 28(1), 192. 10.1007/s10791-025-09604-3
dc.identifier.doi10.1007/s10791-025-09604-3
dc.identifier.issn2948-2992
dc.identifier.issue1
dc.identifier.scopus2-s2.0-105015559342
dc.identifier.scopusqualityQ2
dc.identifier.urihttps://hdl.handle.net/20.500.12939/5951
dc.identifier.volume28
dc.identifier.wosWOS:001567779400001
dc.indekslendigikaynakScopus
dc.indekslendigikaynakWeb of Science
dc.institutionauthorAl-Sharea, Sara AbdulHaleem Nori
dc.institutionauthorÇevik, Mesut
dc.language.isoen
dc.publisherSpringer Science and Business Media B.V.
dc.relation.ispartofDiscover Computing
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Öğrenci
dc.rightsinfo:eu-repo/semantics/openAccess
dc.subject5 × 5 mesh network
dc.subject5 × 5 Network on chip router
dc.subjectAES
dc.subjectCryptography
dc.subjectFPGA
dc.subjectHash algorithm
dc.subjectHash function
dc.subjectKeccak hash function
dc.subjectMobile application
dc.subjectSha-3
dc.subjectSponge function
dc.titleDesign and optimization of 5 × 5 Network on the securing router with integrated SHA-3 & AES core in FPGA for wearable applications
dc.typeArticle

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